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DTSTART;TZID=Europe/Rome:20250214T143000
DTEND;TZID=Europe/Rome:20250214T153000
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UID:49884-1739543400-1739547000@www.isislab.it
SUMMARY:Seminar by  Mohammad Vazirpanah: "A Performance Analysis of Autovectorization on RVV RISC-V Boards" and Seminar by Giuseppe Pagano: "A Quantitative Analysis of Power of Two Quantization on Modern Hardware"
DESCRIPTION:Seminar by  Mohammad Vazirpanah: "A Performance Analysis of Autovectorization on RVV RISC-V Boards" \n\n\n\nAbstract: "The RISC-V instruction set architecture has become increasingly popular due to its open source and extensible design\, making it a competitive choice in high-performance computing and embedded systems. The RISC-V Vector extension (RVV) empowers RISC-V processors with length-agnostic vectorization capabilities\, a critical feature for efficiently handling parallel processing demands across different hardware. Compiler support for autovectorization allows to generate vector instructions automatically without requiring any effort to programmers. Given the limited yet evolving compiler support for RVV\, this paper offers an in-depth examination of autovectorization capabilities in GCC and LLVM\, for RVV version 0.7 and 1.0. We evaluated the autovectorization performance of LLVM\, LLVM-EPI and GCC compilers across 151 loops from the Test Suite for VectorizingCompilers (TSVC) ans seven real-world applications on the All-Winner D1 and BananaPi-F3 boards\, representing RISC-V vector hardware. Our study focuses on quantifying and comparing the level of vectorization each compiler achieves across a diverse range of vectorization patterns and workloads\, providing insight into their strengths and limitations with respect to RISC-V RVV. \n\n\n\nOur findings highlight that the LLVM-19 compiler outperforms GCC-14 in 76 out of 151 loops\, and its performance is more sensitive to the selection of vector length. Additionally\, tuning the vector Length Multiplier (LMUL) parameter can lead to performance improvements of up to 3x\, and leveraging knowledge of the vector length can further enhance LMUL optimization in compilers." \n\n\n\nSeminar by Giuseppe Pagano: "A Quantitative Analysis of Power of Two Quantization on Modern Hardware" \n\n\n\nAbstract: " The rising use of AI in the last few years has greatly reshaped day-to-day productivity in many industries and caused a surge in the demand for AI-capable hardware. To reduce the imposing requirements that running a state of the art model entails many quantization techniques have been introduced.Among them there is Power of Two Quantization (PoTQ) a novel quantization technique that replaces multiplications with bitwise shifts operations. \n\n\n\nIn this seminar we'll go over the details of PoTQ\, the algorithms used to leverage it in order to improve performance thanks to it and what are the plans to measure its impact on modern hardware."
URL:https://www.isislab.it/event/seminar-by-mohammad-vazirpanah-a-performance-analysis-of-autovectorization-on-rvv-risc-v-boards-and-seminar-by-giuseppe-pagano-a-quantitative-analysis-of-power-of-two-quantization-o/
CATEGORIES:Seminari
ATTACH;FMTTYPE=image/png:https://www.isislab.it/wp-content/uploads/2025/02/Seminar-2025-02-14.png
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